SAM-D21G_14 Datasheet, PDF (13/23 Pages) ATMEL Corporation – SMART ARM-Based Microcontroller

6. Processor And Architecture
6.1 Cortex M0+ Processor
The Atmel | SMART SAM D21 implements the ARM^® Cortex™-M0+ processor, which is based on the ARMv6
Architecture and Thumb^®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0
processor, and upward compatible to Cortex-M3 and M4 processors.
For more information refer to www.arm.com.
6.1.1 Cortex M0+ Configuration
Features
Interrupts
Data endianness
SysTick timer
Number of watchpoint comparators
Number of breakpoint comparators
Halting debug support
Multiplier
Single-cycle I/O port
Wake-up interrupt controller
Vector Table Offset Register
Unprivileged/Privileged support
Memory Protection Unit
Reset all registers
Instruction fetch width
Configuration option
External interrupts 0-32
Little-endian or big-endian
Present or absent
0, 1, 2
0, 1, 2, 3, 4
Present or absent
Fast or small
Present or absent
Supported or not supported
Present or absent
Present or absent
Not present or 8-region
Present or absent
16-bit only or mostly 32-bit
Atmel | SMART SAM D21
configuration
32
Little-endian
Present
2
4
Present
Fast (single cycle)
Present
Not supported
Present
Absent⁽¹⁾
Not present
Absent
32-bit
Note: 1. All software run in privileged mode only
The ARM Cortex-M0+ core has two bus interfaces:
z Single 32-bit AMBA^®-3 AHB-Lite™ system interface that provides connections to peripherals and all system
memory, including flash and RAM
z Single 32-bit I/O port bus interfacing to the PORT with one-cycle loads and stores
Atmel | SMART SAM D21 [DATASHEET SUMMARY] 13
Atmel-42181DS–SAM-D21_Summary–09/2014