ATMEGA165P_14 Datasheet, PDF (127/364 Pages) ATMEL Corporation – High Performance, Low Power Atmel

ATmega165P
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f_ExtClk < f_{clk_I/O}/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f_{clk_I/O}/2.5.
An external clock source can not be prescaled.
Figure 15-2. Prescaler for Timer/Counter0 and Timer/Counter1⁽¹⁾
clk_I/O
Clear
PSR10
T0
Synchronization
T1
Synchronization
clk_T1
clk_T0
Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 15-1 on page 126.
8019K–AVR–11/10
127