ATTINY87-A15XZ Datasheet, PDF (123/283 Pages) ATMEL Corporation – Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller

ATtiny87/ATtiny167
or toggle at a compare match (See ”Compare Match Output Unit” on page 120.). The OCnxi
bits over control the setting of the COM1A/B1:0 bits as shown in Figure 12-6 on page 122.
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 130.
12.9.1
Normal Mode
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in
the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer over-
flow interrupt that automatically clears the TOV1 flag, the timer resolution can be increased by
software. There are no special cases to consider in the Normal mode, a new counter value
can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the inter-
val between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
12.9.2
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero
when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1
(WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its res-
olution. This mode allows greater control of the compare match output frequency. It also
simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 12-7. The counter value (TCNT1)
increases until a compare match occurs with either OCR1A or ICR1, and then counter
(TCNT1) is cleared.
Figure 12-7. CTC Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnAi
(Toggle)
Period
1
2
3
4
(COMnA1:0 = 1)
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