ATXMEGA128D4 Datasheet, PDF (12/100 Pages) ATMEL Corporation – 8/16-bit AVR XMEGA D4 Microcontroller

XMEGA D4
7.4 Data Memory
The Data Memory containts the I/O Memory, EEPROM and SRAM memories, all within one lin-
ear address space, see Figure 7-2 on page 12. To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2. Data Memory Map (Hexadecimal address)
Byte Address
ATxmega64D4
Byte Address
0
I/O Registers
0
FFF
(4KB)
FFF
1000
17FF
EEPROM
(2K)
1000
13FF
RESERVED
2000
2FFF
Internal SRAM
(4 KB)
2000
2FFF
ATxmega32D4
I/O Registers
(4KB)
EEPROM
(1 KB)
RESERVED
Internal SRAM
(4 KB)
Byte Address
0
FFF
1000
13FF
2000
27FF
ATxmega16D4
I/O Registers
(4KB)
EEPROM
(1 KB)
RESERVED
Internal SRAM
(2 KB)
7.4.1
7.4.2
Byte Address
0
FFF
1000
17FF
2000
3FFF
ATxmega128D4
I/O Registers
(4 KB)
EEPROM
(2K)
RESERVED
Internal SRAM
(8K)
I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA D4 is shown in the ”Periph-
eral Module Address Map” on page 50.
SRAM Data Memory
The XMEGA D4 devices have internal SRAM memory for data storage.
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