ATAR092_14 Datasheet, PDF (12/107 Pages) ATMEL Corporation – Bi-phase-, Manchester- and Pulse-width Modulator and Demodulator

Figure 4-8. Brown-out Detection
V_DD
2.0V
1.7V
CPU
Reset
CPU
Reset
t_d
BOT = 1
t_d
t
t_d
BOT = 0
t_d = 1.5 ms (Typically)
BOT = 1, Low Brown-out Voltage Threshold 1.7V (Reset Value).
BOT = 0, High Brown-out Voltage Threshold 2.0V.
4.3.2
Watchdog Reset
The watchdog’s function can be enabled at the WDC-register and triggers a reset with every
watchdog counter overflow. To suppress the watchdog reset, the watchdog counter must be
regularly reset by reading the watchdog register address (CWD). The CPU reacts in exactly the
same manner as a reset stimulus from any of the above sources.
4.3.3
External Clock Supervisor
The external input clock supervisor function can be enabled if the external input clock is selected
within the CM- and SC-registers of the clock module. The CPU reacts in exactly the same man-
ner as a reset stimulus from any of the above sources.
4.4 Voltage Monitor
The voltage monitor consists of a comparator with internal voltage reference. It is used to super-
vise the supply voltage or an external voltage at the VMI-pin. The comparator for the supply
voltage has three internal programmable thresholds one lower threshold (2.2V), one middle
threshold (2.6V). and one higher threshold (3.0V). For external voltages at the VMI-pin, the com-
parator threshold is set to V_BG = 1.3V. The VMS-bit indicates if the supervised voltage is below
(VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated when the VMS-bit is
set or reset to detect a rising or falling slope. A voltage monitor interrupt (INT7) is enabled when
the interrupt mask bit (VIM) is reset in the VMC-register.
12 ATAR092/ATAR892
4535E–4BMCU–05/07