ATA5760 Datasheet, PDF (12/41 Pages) ATMEL Corporation – UHF ASK/FSK Receiver

8.2 Bit-check Mode
In bit-check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distances between 2 signal edges are continuously compared to a pro-
grammable time window. The maximum count of this edge-to-edge tests before the receiver
switches to receiving mode is also programmable.
8.3 Configuring the Bit Check
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verify-
ing one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The
maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N_Bit-check in
the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If N_Bit-check
is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the
presence of a valid transmitter signal, the bit check takes less time if N_Bit-check is set to a lower
value. In polling mode, the bit-check time is not dependent on N_Bit-check. Figure 8-2 on page 11
shows an example where 3 bits are tested successfully and the data signal is transferred to pin
DATA.
According to Figure 8-3, the time window for the bit check is defined by two separate time limits.
If the edge-to-edge time t_ee is in between the lower bit-check limit T_{Lim_min} and the upper
bit-check limit T_{Lim_max}, the check will be continued. If t_ee is smaller than T_{Lim_min} or t_ee exceeds
T_{Lim_max}, the bit check will be terminated and the receiver switches to sleep mode.
Figure 8-3.
Valid Time Window for Bit Check
1/f_Sig
Dem_out
t_ee
T_{Lim_min}
T_{Lim_max}
For best noise immunity it is recommended to use a low span between T_{Lim_min} and T_{Lim_max}.
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good choice concerning that
advice. A good compromise between receiver sensitivity and susceptibility to noise is a time win-
dow of ±30% regarding the expected edge-to-edge time t_ee. Using pre-burst patterns that
contain various edge-to-edge time periods, the bit-check limits must be programmed according
to the required span.
The bit-check limits are determined by means of the formula below.
T_{Lim_min} = Lim_min × T_XClk
T_{Lim_max} = (Lim_max – 1) × T_XClk
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
12 ATA5760/ATA5761
4896C–RKE–04/06