ATMEGA325_0611 Datasheet, PDF(118/353 Page) ATMEL Corporation – 8-bit Microcontroller with In-System Programmable Flash

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ATMEGA325_0611 Datasheet, PDF (118/353 Pages) ATMEL Corporation – 8-bit Microcontroller with In-System Programmable Flash

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Timer/Counter Timing

Diagrams

non-inverted PWM and an inverted PWM output can be generated by setting the

COM1x1:0 to three (See Table 1 on page 121). The actual OC1x value will only be visi-

ble on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The

PWM waveform is generated by setting (or clearing) the OC1x Register at the compare

match between OCR1x and TCNT1 when the counter increments, and clearing (or set-

ting) the OC1x Register at compare match between OCR1x and TCNT1 when the

counter decrements. The PWM frequency for the output when using phase and fre-

quency correct PWM can be calculated by the following equation:

fOCnxPFCPWM

=

------f--c---l-k--_---I-/-O--------

2 â N â TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating

a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to

BOTTOM the output will be continuously low and if set equal to TOP the output will be

set to high for non-inverted PWM mode. For inverted PWM the output will have the

opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and

COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.

The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when Interrupt Flags are set, and when the OCR1x Register is updated with the

OCR1x buffer value (only for modes utilizing double buffering). Figure 50 shows a timing

diagram for the setting of OCF1x.

Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling

clkI/O

clkTn

(clkI/O/1)

TCNTn

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx

OCRnx Value

OCFnx

Figure 51 shows the same timing data, but with the prescaler enabled.

118 ATmega325/3250/645/6450

2570JâAVRâ11/06

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