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ATMEGA16L_14 Datasheet, PDF (115/357 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments | |||
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ATmega16(L)
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See âAccessing 16-bit Registersâ on page 92.
Timer/Counter
Interrupt Mask
Register â TIMSK(1)
Bit
Read/Write
Initial Value
7
OCIE2
R/W
0
6
TOIE2
R/W
0
5
TICIE1
R/W
0
4
OCIE1A
R/W
0
3
OCIE1B
R/W
0
2
TOIE1
R/W
0
1
OCIE0
R/W
0
0
TOIE0
R/W
0
TIMSK
Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
described in this section. The remaining bits are described in their respective timer sections.
⢠Bit 5 â TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt
Vector (See âInterruptsâ on page 45.) is executed when the ICF1 Flag, located in TIFR, is set.
⢠Bit 4 â OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding
Interrupt Vector (See âInterruptsâ on page 45.) is executed when the OCF1A Flag, located in
TIFR, is set.
⢠Bit 3 â OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding
Interrupt Vector (See âInterruptsâ on page 45.) is executed when the OCF1B Flag, located in
TIFR, is set.
⢠Bit 2 â TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector
(See âInterruptsâ on page 45.) is executed when the TOV1 Flag, located in TIFR, is set.
Timer/Counter
Interrupt Flag Register
â TIFR
Bit
Read/Write
Initial Value
7
OCF2
R/W
0
6
TOV2
R/W
0
5
ICF1
R/W
0
4
OCF1A
R/W
0
3
OCF1B
R/W
0
2
TOV1
R/W
0
1
OCF0
R/W
0
0
TOV0
R/W
0
TIFR
Note: This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in
this section. The remaining bits are described in their respective timer sections.
2466TâAVRâ07/10
115
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