ATMEGA16 Datasheet, PDF (112/315 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 16K Bytes In-System Programmable Flash

Definitions
Timer/Counter Clock
Sources
Counter Unit
The double buffered Output Compare Register (OCR2) is compared with the
Timer/Counter value at all times. The result of the compare can be used by the wave-
form generator to generate a PWM or variable frequency output on the Output Compare
Pin (OC2). See “Output Compare Unit” on page 113. for details. The compare match
event will also set the Compare Flag (OCF2) which can be used to generate an output
compare interrupt request.
Many register and bit references in this document are written in general form. A lower
case “n” replaces the Timer/Counter number, in this case 2. However, when using the
register or bit defines in a program, the precise form must be used (i.e., TCNT2 for
accessing Timer/Counter2 counter value and so on). The definitions in Table 49 are also
used extensively throughout the document.
Table 49. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal
255).
TOP
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR2 register. The
assignment is dependent on the mode of operation.
The Timer/Counter can be clocked by an internal synchronous or an external asynchro-
nous clock source. The clock source clk_T2 is by default equal to the MCU clock, clk_I/O.
When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken
from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on
asynchronous operation, see “Asynchronous Status Register – ASSR” on page 124. For
details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 127.
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
Figure 54 shows a block diagram of the counter and its surrounding environment.
Figure 54. Counter Unit Block Diagram
DATA BUS
TOVn
(Int.Req.)
TCNTn
count
clear
direction
Control Logic
clk _Tn
Prescaler
bottom
top
Signal description (internal signals):
count
Increment or decrement TCNT2 by 1.
direction Selects between increment and decrement.
clear
Clear TCNT2 (set all bits to zero).
clk_T2
Timer/Counter clock.
T/C
Oscillator
TOSC1
TOSC2
clk
I/O
112 ATmega16(L)
2466E–AVR–10/02