ATMEGA649_14 Datasheet, PDF (111/392 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

ATmega329/3290/649/6490
Figure 16-1. 16-bit Timer/Counter Block Diagram⁽¹⁾
Count
Clear
Direction
Control Logic
clk_Tn
Timer/Counter
TCNTn
TOP BOTTOM
=
=0
=
OCRnA
=
OCRnB
ICRn
TCCRnA
Fixed
TOP
Values
ICFn (Int.Req.)
Edge
Detector
TCCRnB
TOVn
(Int.Req.)
Clock Select
Edge
Detector
( From Prescaler )
OCnA
(Int.Req.)
Waveform
Generation
Tn
OCnA
OCnB
(Int.Req.)
Waveform
Generation
OCnB
( From Analog
Comparator Ouput )
Noise
Canceler
ICPn
16.2.1 Registers
Note: 1. Refer to Figure 1-1 on page 2, Table 13-5 on page 68, and Table 13-11 on page 72 for
Timer/Counter1 pin placement and description.
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis-
ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These procedures are described in the section “Accessing 16-bit Registers” on
page 113. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no
CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all
visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with
the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk_T1).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Coun-
ter value at all time. The result of the compare can be used by the Waveform Generator to
generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See “Out-
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