ATMEGA168P_14 Datasheet, PDF (110/420 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 15-8, ”Waveform
Generation Mode Bit Description” on page 106.
110 ATmega48P/88P/168P
8025M–AVR–6/11