AT68166F_14 Datasheet, PDF (11/16 Pages) ATMEL Corporation – TTL-Compatible Inputs and Outputs

Read Cycle
Read Cycle 1
Read Cycle 2
AT68166F
Table 5. Read cycle timings⁽¹⁾
AT68166F-20
AT68166F-18
Symbol
TAVAV
TAVQV
TAVQX
TELQV
TELQX
TEHQZ
TGLQV
TGLQX
TGHQZ
Parameter
Read cycle time
Address access time
Address valid to low Z
Chip-select access time
CS low to low Z⁽²⁾
CS high to high Z⁽²⁾
Output Enable access time
OE low to low Z⁽²⁾
OE high to high Z ⁽²⁾
min
max
min
max
Unit
20
-
18
-
ns
-
20
-
18
ns
5
-
5
-
ns
-
20
-
18
ns
5
-
5
-
ns
-
9
-
8
ns
-
11
-
8
ns
2
-
2
-
ns
-
9
-
8
ns
Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Wave-
forms” on page 9.)
Address Controlled (CS = OE = V_IL, WE = V_IH)
ADDRESS
DOUT
Chip Select Controlled (WE = V_IH)
CSx
OE
DOUT
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