ATXMEGA256A3_1012 Datasheet, PDF (108/134 Pages) ATMEL Corporation – 8/16-bit XMEGA A3 Microcontroller

XMEGA A3
4. Flash Power Reduction Mode can not be enabled when entering sleep mode
If Flash Power Reduction Mode is enabled when a deep sleep mode, the device will only
wake up on every fourth wake-up request.
If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time
will vary with up to 16 CPU clock cycles.
Problem fix/Workaround
Disable Flash Power Reduction mode before entering sleep mode.
5. JTAG enable does not override Analog Comparator B output
When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT
on pin 7 if this is enabled.
Problem fix/Workaround
AC0OUT for ACB should not be enabled when JTAG is used. Use only analog comparator
output for ACA when JTAG is used, or use the PDI as debug interface.
6. Bandgap measurement with the ADC is non-functional when V_CC is below 2.7V
The ADC cannot be used to do bandgap measurements when V_CC is below 2.7V.
Problem fix/Workaround
If internal voltages must be measured when V_CC is below 2.7V, measure the internal 1.00V
reference instead of the bandgap.
7. DAC refresh may be blocked in S/H mode
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workarund
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
8. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
9. Both DFLLs and both oscillators has to be enabled for one to work
In order to use the automatic runtime calibration for the 2 MHz or the 32MHz internal oscilla-
tors, the DFLL for both oscillators and both oscillators has to be enabled for one to work.
Problem fix/Workaround
Enable both the DFLLs and both oscillators when using automatic runtime calibration for
one of the internal oscillators.
8068T–AVR–12/10
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