ATTINY87 Datasheet, PDF (107/282 Pages) ATMEL Corporation – 8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller

ATtiny87/ATtiny167
11. Timer/Counter1 Prescaler
11.1 Overview
Most bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number.
11.1.1
11.1.2
Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f_{CLK_I/O}). Alternatively, one of four taps from the prescaler can be
used as a clock source. The prescaled clock has a frequency of either f_{CLK_I/O}/8, f_{CLK_I/O}/64,
f_{CLK_I/O}/256, or f_{CLK_I/O}/1024.
Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the
state of the prescaler will have implications for situations where a prescaled clock is used. One
example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler
(6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the
first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler
divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it
is connected to.
11.1.3
External Clock Source
An external clock source applied to the T1 pin can be used as Timer/Counter clock (clk_T1).
The T1 pin is sampled once every system clock cycle by the pin synchronization logic. The
synchronized (sampled) signal is then passed through the edge detector. Figure 11-1 shows a
functional equivalent block diagram of the T1 synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (clk_I/O). The latch is
transparent in the high period of the internal system clock.
The edge detector generates one clk_T1 pulse for each positive (CSn2:0 = 7) or negative
(CSn2:0 = 6) edge it detects.
Figure 11-1. T1 Pin Sampling
Tn
clk_I/O
DQ
LE
DQ
Synchronization
DQ
Tn_sync
(To Clock
Select Logic)
Edge Detector
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