AT89C51SND2C_14 Datasheet, PDF (106/242 Pages) ATMEL Corporation – Bass, Medium, and Treble Control (31 Steps)

Figure 16-5. UFI Block Diagram
12 MHz DPLL
Transfer
Control
FSM
Asynchronous Information
USBCON
USBADDR
USBINT
USBIEN
UEPNUM
UEPCONX
UEPSTAX
UEPRST
UEPINT
UEPIEN
UEPDATX
UBYCTX
UFNUMH
UFNUML
To/From C51 Core
To/From SIE
Endpoint Control
USB side
Endpoint 2
Endpoint 1
Endpoint 0
Endpoint Control
C51 side
Figure 16-6. USB Typical Transaction Load
OUT Transactions:
HOST
UFI
C51
OUT
DATA0 (n Bytes)
OUT DATA1
ACK C51 interrupt
NACK
Endpoint FIFO read (n Bytes)
IN Transactions:
HOST
UFI
C51
IN
IN
NACK
Endpoint FIFO Write
DATA1
IN
DATA1
OUT DATA1
ACK
ACK
C51 interrupt
Endpoint FIFO write
106 AT8xC51SND2C/MP3B
4341H–MP3–10/07