AT89C51ID2_14 Datasheet, PDF (106/157 Pages) ATMEL Corporation – Six 8-bit I/O Ports (64 pins or 68 Pins Versions)

AT89C51ID2
Bit
Bit
Number Mnemonic Description
Reserved
1
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
0
-
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 00X0 XXXXb
Not Bit addressable
Serial Peripheral DATa Register
(SPDAT)
The Serial Peripheral Data Register (Table 81) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer is
available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 81. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
Table 3.
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
Reset Value = Indeterminate
R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there
is no on-going exchange. However, special care should be taken when writing to them
while a transmission is on-going:
• Do not change SPR2, SPR1 and SPR0
• Do not change CPHA and CPOL
• Do not change MSTR
• Clearing SPEN would immediately disable the peripheral
• Writing to the SPDAT will cause an overflow.
4289C–8051–11/05
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