ATA8743_14 Datasheet, PDF (104/215 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

21.7.2 Compare Match Blocking by TCNT1 Write
All CPU writes to the TCNT1 register will block any compare match that occurs in the next timer clock cycle, even when the
timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt
when the Timer/Counter clock is enabled.
21.7.3 Using the Output Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks
involved when changing TCNT1 when using any of the output compare channels, independent of whether the Timer/Counter
is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will be missed, resulting in
incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The
compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value
equal to BOTTOM when the counter is downcounting.
The setup of the OC1x should be performed before setting the data direction register for the port pin to output. The easiest
way of setting the OC1x value is to use the force output compare (1x) strobe bits in normal mode. The OC1x register keeps
its value even when changing between waveform generation modes.
Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will
take effect immediately.
21.8
Compare Match Output Unit
The compare output mode (COM1x1:0) bits have two functions. The waveform generator uses the COM1x1:0 bits for
defining the output compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin
output source. Figure 21-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O registers,
I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT)
that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x
register, not the OC1x pin. If a system reset occur, the OC1x register is reset to “0”.
Figure 21-5. Compare Match Output Unit, Schematic
COMnx1
COMnx0
FOCn
Waveform
Generator
D
Q
1
OCnx
0
D
Q
PORT
D
Q
clk_I/O
DDR
OCnx
Pin
104 ATA8743 [DATASHEET]
9152D–INDCO–09/14