AT89LP3240_14 Datasheet, PDF (103/200 Pages) ATMEL Corporation – Nonvolatile Program and Data Memory

AT89LP3240/6440
Symbol Function
SPI clock rate select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no
effect on the slave. The relationship between SCK and the oscillator frequency, F_OSC., is as follows:
SPR1 SPR0 SCK (TSCK = 0) SCK (TSCK = 1)
SPR0
SPR1
0
0
f_OSC/4
0
1
f_OSC/8
f_T1OVF/4
f_T1OVF/8
1
0
f_OSC/32
f_T1OVF/32
1
1
f_OSC/64
f_T1OVF/64
Notes: 1. Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE.
2. Enable the master SPI prior to the slave device.
3. Slave echoes master on the next Tx if not loaded with new data.
Table 17-3. SPDR – SPI Data Register
SPDR Address = EAH
Not Bit Addressable
Reset Value = 00H (after cold reset)
unchanged (after warm reset)
SPD7
Bit
7
SPD6
6
SPD5
5
SPD4
4
SPD3
3
SPD2
2
SPD1
1
SPD0
0
Table 17-4. SPSR – SPI Status Register
SPSR Address = E8H
Not Bit Addressable
Reset Value = 0000 X000B
SPIF
Bit
7
WCOL
6
MODF
5
TXE
4
–
SSIG
DISSO
ENH
3
2
1
0
Symbol
SPIF
WCOL
MODF
TXE
Function
SPI Transfer Complete Interrupt Flag. When a serial transfer is complete, the SPIF bit is set by hardware and an interrupt
is generated if ESP = 1. The SPIF bit may be cleared by software or by reading the SPI status register followed by
reading/writing the SPI data register.
Write Collision Flag. The WCOL bit is set by hardware if SPDR is written while the transmit buffer is full. The ongoing
transfer is not affected. WCOL may be cleared by software or by reading the SPI status register followed by
reading/writing the SPI data register.
Mode Fault Flag. MODF is set by hardware when a master mode collision is detected (MSTR = 1, SSIG = 0 and SS = 0)
and an interrupt is generated if ESP = 1. MODF must be cleared by software.
Transmit Buffer Empty Flag. Set by hardware when the transmit buffer is loaded into the shift register, allowing a new byte
to be loaded. TXE must be cleared by software. When ENH = 1 and ESP = 1, TXE will generate an interrupt.
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