ATMEGA325P_06 Datasheet, PDF (102/336 Pages) ATMEL Corporation – 8-bit Microcontroller with 32K Bytes In-System Programmable Flash

The edge detector generates one clk_T1/clk_T0 pulse for each positive (CSn2:0 = 7) or negative
(CSn2:0 = 6) edge it detects.
Figure 13-8. T1/T0 Pin Sampling
Tn
clk_I/O
DQ
LE
DQ
Synchronization
DQ
Tn_sync
(To Clock
Select Logic)
Edge Detector
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f_ExtClk < f_{clk_I/O}/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f_{clk_I/O}/2.5.
An external clock source can not be prescaled.
Figure 13-9. Prescaler for Timer/Counter0 and Timer/Counter1⁽¹⁾
clk_I/O
Clear
PSR10
T0
Synchronization
T1
Synchronization
clk_T1
clk_T0
Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 13-8.
102 ATmega325P/3250P
8023A–AVR–12/06