ATA5771 Datasheet, PDF (102/284 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

9.3 Register Description
9.3.1
MCUCR – MCU Control Register
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit
0x35 (0x55)
Read/Write
Initial Value
7
BODS
R/W
0
6
PUD
R/W
0
5
SE
R/W
0
4
SM1
R/W
0
3
SM0
R/W
0
2
BODSE
R/W
0
1
ISC01
R/W
0
0
ISC00
R/W
0
MCUCR
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 9-2. The value on the INT0 pin is sampled before detecting edges.
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-2.
ISC01
0
0
1
1
Interrupt 0 Sense Control
ISC00 Description
0
The low level of INT0 generates an interrupt request.
1
Any logical change on INT0 generates an interrupt request.
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
9.3.2 GIMSK – General Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
0x3B (0x5B)
–
INT0
PCIE1
PCIE0
–
–
–
–
GIMSK
Read/Write
R
R/W
R/W
R/w
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
• Bits 7, 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT11..8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT11..8 pins are enabled individually by the PCMSK1 Register.
50 ATtiny24/44/84
8006G–AVR–01/08