AT89C51IC2_14 Datasheet, PDF (100/147 Pages) ATMEL Corporation – During UART Reception, Clearing REN may Generate Unexpected IT

Bit
Number
1
0
Bit
Mnemonic Description
SD1 Address bit 1 or Data bit 1.
SD0 Address bit 0 (R/W) or Data bit 0.
Table 75. SSCS (094h) read - Synchronous Serial Control and Status Register
7
6
5
4
3
2
1
0
SC4
SC3
SC2
SC1
SC0
0
0
0
Table 76. SSCS Register: Read Mode - Reset Value = F8h
Bit
Bit
Number Mnemonic Description
0
0
Always zero
1
0
Always zero
2
0
Always zero
3
SC0
Status Code bit 0
See Table 68.to Table 72.
Status Code bit 1
4
SC1
See Table 68.to Table 72.
5
SC2
Status Code bit 2
See Table 68.to Table 72.
6
SC3
Status Code bit 3
See Table 68.to Table 72.
7
SC4
Status Code bit 4
See Table 68.to Table 72.
100 AT89C51IC2
4301D–8051–02/08