ATMEGA6450V_14 Datasheet, PDF (10/362 Pages) ATMEL Corporation – High Endurance Non-volatile Memory Segments

ATmega325/3250/645/6450
7. AVR CPU Core
7.1 Overview
This section discusses the Atmel^® AVR^® core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to access
memories, perform calculations, control peripherals, and handle interrupts.
7.2 Architectural Overview
Figure 7-1. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
Data
SRAM
EEPROM
I/O Module1
I/O Module 2
I/O Module n
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
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2570N–AVR–05/11