ATMEGA169PA_14 Datasheet, PDF (10/39 Pages) ATMEL Corporation – 8-bit Atmel Microcontroller with 16/32/64KB In-System Programmable Flash

are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 79.
2.3.8
Port F (PF7...PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal
pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not
running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be
activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.3.9
Port G (PG5...PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated
when a reset condition becomes active, even if the clock is not running.
Port G also serves the functions of various special features of the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 83.
2.3.10 Port H (PH7...PH0)
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Port H also serves the functions of various special features of the ATmega3290PA/6490P as listed on page 85.
2.3.11 Port J (PJ6...PJ0)
Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port J also serves the functions of various special features of the ATmega3290PA/6490P as listed on page 87.
2.3.12 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running. The minimum pulse length is given in ”System and reset characteristics” on page 332. Shorter
pulses are not guaranteed to generate a reset.
2.3.13 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.14 XTAL2
Output from the inverting Oscillator amplifier.
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 10
8284FS–AVR–07/2014