ATMEGA161_07 Datasheet, PDF (10/159 Pages) ATMEL Corporation – 8-bit Microcontroller with 16K Bytes of In-System Programmable Flash

The General Purpose
Register File
Figure 6 shows the structure of the 32 general purpose working registers in the CPU.
Figure 6. AVR CPU General Purpose Working Registers
General
Purpose
Working
Registers
7
0
R0
R1
R2
…
R13
R14
R15
R16
R17
…
R26
R27
R28
R29
R30
R31
Addr.
$00
$01
$02
$0D
$0E
$0F
$10
$11
$1A
$1B
$1C
$1D
$1E
$1F
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
All the register operating instructions in the instruction set have direct and single cycle
access to all registers. The only exceptions are the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and
the LDI instruction for load immediate constant data. These instructions apply to the
second half of the registers in the Register File – R16..R31. The general SBC, SUB, CP,
AND, and OR, and all other operations between two registers or on a single register
apply to the entire Register File.
As shown in Figure 6, each register is also assigned a Data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being phys-
ically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any
register in the file.
The X-register, Y-register and The registers R26..R31 have some added functions to their general purpose usage.
Z-register
These registers are address pointers for indirect addressing of the Data Space. The
three indirect address registers X, Y, and Z are defined as:
Figure 7. X-, Y-, and Z-registers
15
0
X-register
7
07
0
R27 ($1B)
R26 ($1A)
15
0
Y-register
7
07
0
R29 ($1D)
R28 ($1C)
15
0
Z-register
7
07
0
R31 ($1F)
R30 ($1E)
10 ATmega161(L)
1228D–AVR–02/07