AT91F40816_02 Datasheet, PDF (10/21 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1 is con-
nected to a device not including this pull-up, the user must make sure that a high level is tied
on NTRI while NRST is asserted.
JTAG/ICE Debug
ARM standard embedded In-circuit emulation is supported via the JTAG/ICE port. The pins
TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host
computer via the external ICE interface.
In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identifies the
microcontroller. This is not fully IEEE1149.1 compliant.
Memory Controller
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the
internal 32-bit address bus and defines three address spaces:
• Internal memories in the four lowest megabytes
• Middle space reserved for the external devices (memory or peripherals) controlled by the
EBI
• Internal peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.
Internal Memories
The AT91F40816 integrates 8K bytes of primary internal SRAM that is 32 bits wide and single-
clock cycle accessible. This SRAM is mapped at address 0x0 (after the remap command),
allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software.
The rest of the SRAM can be used for stack allocation (to speed up context saving and restor-
ing), or as data and program storage for critical algorithms. Byte (8-bit), half-word (16-bit) or
word (32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or
ARM instructions is supported and internal memory can store twice as many Thumb instruc-
tions as ARM ones.
The AT91F40816 also integrates a 2-Mbyte Flash memory that is accessed via the External
Bus Interface. All data, address and control lines, except for the Chip Select signal, are con-
nected within the device. Byte and half-word accesses are supported.
Boot Mode Select
The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-
cutes the instruction stored at this address. This means that this address must be mapped in
nonvolatile memory after the reset.
The input level on the BMS pin during the last 10 clock cycles before the rising edge of the
NRST selects the type of boot memory (see Table 3). If the embedded Flash memory is to be
used as boot memory, the BMS input must be pulled down externally.
The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any
standard PIO line.
Table 3. Boot Mode Select
BMS
Boot Memory
1
External 8-bit memory on NCS0
0
External 16-bit memory on NCS0
Remap Command
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,
Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors
to be redefined dynamically by the software, the AT91F40816 uses a remap command that
enables switching between the boot memory and the internal primary SRAM addresses. The
remap command is accessible through the EBI User Interface by writing one in RCB of
10 AT91F40816
1384C–ATARM–02/02