AT43301_05 Datasheet, PDF (10/27 Pages) ATMEL Corporation – Low-cost USB Hub Controller

Each bit in the Status Change Register corresponds to one port as shown below:
Table 2-2. Status Change Register
Bit Function
0
Hub status change
1
Port1 status change
2
Port2 status change
3
Port3 status change
4
Port4 status change
5-7 Reserved
Value
0
1
0
1
0
1
0
1
0
1
000
Meaning
No change in status
Change in status detected
No change in status
Change in status detected
No change in status
Change in status detected
No change in status
Change in status detected
No change in status
Change in status detected
Default values
An IN Token packet from the host to Endpoint 1 indicates a request for port change status. If the
hub has not detected any change on its ports, or any changes in itself, then all bits in this regis-
ter will be 0 and the Hub Controller will return a NAK to requests on Endpoint1. If any of bits 0-4
is 1, the Hub Controller will transfer the whole byte. The Hub Controller will continue to report a
status change when polled until that particular change has been removed by a ClearPortFeature
request from the Host. No status change will be reported by Endpoint 1 until the AT43301 has
been enumerated and configured by the host.
2.7 Oscillator and Phase-Locked-Loop
All the clock signals required to run the AT43301 are derived from an on-chip oscillator. To
reduce EMI and power dissipation in the system, the AT43301 is designed to operate with a 6
MHz crystal. An on-chip PLL generates the high frequency for the clock/data separator of the
Serial Interface Engine. In the suspended state, the oscillator circuitry is turned off. To assure
quick startup, a crystal with a high Q, or low ESR, should be used. To meet the USB hub fre-
quency accuracy and stability requirements for hubs, the crystal should have an accuracy and
stability of better than 100 ppm. Even though the oscillator circuit would work with a ceramic res-
onator, its use is not recommended because a resonator would not have the frequency accuracy
and stability.
A 6 MHz parallel resonance quartz crystal with a load capacitance of approximately 10 pF is rec-
ommended. The oscillator is a special low-power design and in most cases no external
capacitors and resistors are necessary. If the crystal requires a higher value capacitance, exter-
nal capacitors can be added to the two terminals of the crystal and ground to meet the required
value. If the crystal used cannot tolerate the drive levels of the oscillator, a series resistor
between OSC2 and the crystal pin is recommended.
The clock can also be externally sourced. In this case, connect the clock source to the OSC1
pin, while leaving OSC2 pin floating. The switching level at the OSC1 pin can be as low as 0.47V
(see “Electrical Specification” on page 12) and a CMOS device is required to drive this pin to
maintain good noise margins at the low switching level. The 32-lead AT43301-AC can also be
driven by a 48 MHz external clock instead. In this case, connect the 48N pin to ground.
10 AT43301
1137J–USB–01/06