AT25F4096 Datasheet, PDF (10/17 Pages) ATMEL Corporation – SPI SERIAL MEMORY 4M

first. The AT25F4096 will automatically return to the write disable state at the completion
of the PROGRAM cycle.
Note:
If the device is not write enabled (WREN), the device will ignore the Write instruction and
will return to the standby state, when CS is brought high. A new CS falling edge is
required to re-initiate the serial communication.
Table 6. Address Key
Address
AT25F4096
A_N
Dont’ Care Bits
A₁₈ - A₀
A₂₃ - A₁₉
SECTOR ERASE (SECTOR ERASE): Before a byte can be reprogrammed, the sector
which contains the byte must be erased. In order to erase the AT25F4096, two separate
instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then the SECTOR ERASE instruction can be executed.
Table 7. Sector Addresses
Sector Address
000000 to 00FFFF
010000 to 01FFFF
020000 to 02FFFF
030000 to 03FFFF
040000 to 04FFFF
050000 to 05FFFF
060000 to 06FFFF
070000 to 07FFFF
AT25F4096 Sector
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
The SECTOR ERASE instruction erases every byte in the selected sector if the sector is
not locked out. Sector address is automatically determined if any address within the sec-
tor is selected. The SECTOR ERASE instruction is internally controlled; it will
automatically be timed to completion. During this time, all commands will be
ignored, except RDSR instruction. The AT25F4096 will automatically return to the write
disable state at the completion of the SECTOR ERASE cycle.
CHIP ERASE (CHIP ERASE): As an alternative to the SECTOR ERASE, the CHIP
ERASE instruction will erase every byte in all sectors that are not locked out. First, the
device must be write enabled via the WREN instruction. Then the CHIP ERASE instruc-
tion can be executed. The CHIP ERASE instruction is internally controlled; it will
automatically be timed to completion. The CHIP ERASE cycle time typically is 8 sec-
onds. During the internal erase cycle, all instructions will be ignored except RDSR. The
AT25F4096 will automatically return to the write disable state at the completion of the
CHIP ERASE cycle.
10 AT25F4096 [Advance Information]
2454C–SEEPR–8/04