TS87C51RB2_14 Datasheet, PDF (1/3 Pages) ATMEL Corporation – UART/Reception in Modes 1, 2 and 3/UART False Start Bits Detection

Active Errata List
• UART/Reception in Modes 1, 2 and 3/UART False Start Bits Detection
• During UART Reception, Clearing REN May Generate Unexpected IT
• JBC/Double IT When External IT Occurs During JBC Instruction
• Timer2/Downcounter Mode/Double IT With Slow External Clock
• Input Trigger Consumption/All C51 Type I/O Ports
• MOVX/Port0/Read Mode
Errata History
AT80C51RA2
Lot Number
All
Errata List
T02,T03,T04,T05,T06
TS80C51RB2
Lot Number
≤ 38584
> 38584
Errata List
T01, T02 ,T03, T04, T05, T06
T02 ,T03, T04, T05, T06
TS87C51RB2
Lot Number
≤ 36425
> 36425
Errata List
T01, T02 ,T03, T04, T05, T06
T02 ,T03, T04, T05, T06
Errata Descriptions
1. UART/Reception in Modes 1, 2 and 3/UART False Start Bits Detection
When a false start bit occurs on the UART, some UART internal signals are not reset.
Then when a real start bit occurs, the sampling is shifted.
Workaround
None.
8051
Microcontrollers
TS87C51RB2
TS80C51RB2
AT80C51RA2
Errata Sheet
2. During UART Reception, Clearing REN May Generate Unexpected IT
During UART reception, if the REN bit is clear between a start bit detection and the
end of reception, the UART will not discard the data (RI is set).
Workaround
Test REN at the beginning of Interrupt routine just after CLR RI, and run the Interrupt
routine code only if REN is set.
4154D–8051–03/08