PC107A Datasheet, PDF (1/50 Pages) ATMEL Corporation – PCI Bridge Memory Controller

Features
• Processor Bus Frequency up to 100 MHz
• 64- or 32-bit Data Bus and 32-bit Address Bus
• Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst
SRAM
• Compliant with PCI Specification, Revision 2.1
• PCI Interface Operates up to 66 MHz/5.0V Compatible
• IEEE 1149.1 Compliant, JTAG Boundary-scan Interface
• PD Max = 1W (66 MHz), Full Operating Conditions
• Nap, Doze and Sleep Modes for Power Savings
• Two-channel Integrated DMA Controller
• Message Unit
– Intelligent Input/Output (Two-wire Interface) Message Controller
– Two Door Bell Registers
– Inbound and Outbound Messaging Registers
• Inter-integrated Circuit (Two-wire Interface) Controller, Full Master/Slave Support
• Embedded Programmable Interrupt Controller (EPIC)
– Five Hardware Interrupts (IRQs) or 16 Serial Interrupts
– Four Programmable Timers
Description
The PC107A PCI Bridge/Integrated Memory Controller provides a bridge between the
Peripheral Component Interconnect, (PCI) bus and PowerPC 603e^™, PowerPC 740^™,
PowerPC 750^™ or PC7400 microprocessors.
PCI support allows system designers to design systems quickly using peripherals
already designed for PCI and other standard interfaces available in the personal com-
puter hardware environment. The PC107A provides many other necessities for
embedded applications including a high-performance memory controller and dual pro-
cessor support, 2-channel flexible DMA controller, an interrupt controller, an I₂O-ready
message unit, an inter-integrated circuit controller (Two-wire Interface), and low skew
clock drivers. The PC107A contains an Embedded Programmable Interrupt Controller
(EPIC) featuring five hardware interrupts (IRQ’s) as well as sixteen serial interrupts
along with four timers. The PC107A uses an advanced, 2.5V HiP3 process technology
and is fully compatible with TTL devices.
PCI Bridge
Memory
Controller
PC107A
Preliminary
Specification
β-site
ZF
PBGA 503
Flip-chip Plastic Ball Grid Array
GH suffix
HITCE 503
Ceramic Ball Grid Array
Screening
This product is manufactured in full compliance with:
• PBGA upscreenings based upon Atmel standards
• Full military temperature range (Tj = -55°C, +125°C)
• Industrial temperature range (Tj = -40°C, +110°C)
• HiTCE (TBC)
Rev. 2137C–HIREL–03/04