MH1 Datasheet, PDF (1/17 Pages) ATMEL Corporation – 1.6M Used Gates 0.35 μm CMOS Sea of Gates/ Embedded Array

Features
• Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries
• High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 (Nominal)
• System Level Integration Technology Cores on Request
• SRAM and TRAM (Gate Level or Embedded)
• I/O Interfaces:
– 5V Tolerant/Compliant (S) or 3V (R) Matrix Options
– CMOS, LVTTL, LVDS, PCI, USB
– Output Currents Programmable from 2 to 24 mA, by Step of 2 mA
• 250 MHz PLL (On Request), 220 MHz LVDS and 800 MHz Max Toggle Frequency at 3.3V
• Deep Submicron CAD Flow
• QML Q with SMD 5962-01B01
Description
The MH1 Gate Array and Embedded Array families from Atmel are fabricated on a
0.35 micron CMOS process, with up to 4 levels of metal. This family features arrays
with up to 1.6 million routable gates and 596 pads. The high density cores and/or high
pin count capabilities of the MH1 family, coupled with the ability to embed memories
on the same silicon, make the MH1 series of arrays one of the best choices for Sys-
tem Level Integration.
The MH1 series is supported by an advanced software environment based on industry
standards linking proprietary and commercial tools. Verilog^®, DFT^®, Synopsys^® and
Vital are the reference front end tools. The Cadence^® ‘Logic Design Planner’ floor
planning associated with timing driven layout provides an efficient back end cycle.
The MH1 series comes as a dual use of the MH1RT series, without the latch up and
total dose immunity features.
The MH1 series comes as the Atmel seventh generation of ASIC series designed for
military and avionics types of applications in a 15-year time frame.
It is also made available to any of the currently available quality grades: commercial,
industrial, automotive and military.
1.6M Used Gates
0.35 µm CMOS
Sea of Gates/
Embedded Array
MH1
Rev. 4138G–AERO–05/04
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