MG2RT_14 Datasheet, PDF (1/13 Pages) ATMEL Corporation – Full Range of Matrices with up to 480K Gates

Features
• Full Range of Matrices with up to 480K Gates
• 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates
• RAM and DPRAM Compilers
• Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG)
• 3 and 5 Volts Operation; Single or Dual Supply Mode
• High Speed Performances:
– 450 ps Max NAND2 Propagation Delay at 4.5V, 720 ps at 2.7V and FO = 5
– Min 610 MHz Toggle Frequency at 4.5V, 320 MHz at 2.7V
• Programmable PLL Available upon Request
• High System Frequency Skew Control through Clock Tree Synthesis Software
• Low Power Consumption:
– 1.96 µW/Gate/MHz at 5V
– 0.6 µW/Gate/MHz at 3V
• Integrated Power On Reset
• Matrices with a Max of 484 Fully Programmable Pads
• Standard 3, 6, 12 and 24 mA I/Os
• Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator
• CMOS/TTL/PCI Interface
• ESD (2 kV) and Latch-up Protected I/O
• High Noise and EMC Immunity:
– I/O with Slew Rate Control
– Internal Decoupling
– Signal Filtering between Periphery and Core
– Application Dependent Supply Routing and Several Independant Supply Sources
• Wide Selection of MQFPs and MCGA Packages up to 472 Pins
• Delivery in Die Form with 94.6 µm Pad Pitch
• Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout,
Power Management
• Cadence^®, Mentor^®, Vital^® and Synopsys^® Reference Platforms
• EDIF and VHDL Reference Formats
• Available in Military and Space Quality Grades (SCC, MIL-PRF-38535)
• No Single Event Latch-up below an LET threshold of 80MeV/mg/cm²
• Tested up to a Total Dose of 60 Krad (Si) according to MIL STD 883 Method 1019
• QML Q and V with SMD 5962-00B02
Rad Tolerant
350K Used Gates
0.5 µm CMOS
Sea of Gates
MG2RT
Description
The MG2RT series is a 0.5 micron, array based, CMOS product family. Several arrays
up to 480K gates cover most system integration needs. The MG2RT is manufactured
using a 0.5 micron drawn, 3 metal layer CMOS process, called SCMOS 3/2RT.
The base cell architecture of the MG2RT series provides high routability of logic with
extremely dense compiled memories: RAM and DPRAM. ROM can be generated
using synthesis tools.
Accurate control of clock distribution can be achieved by PLL hardware and CTS
(Clock Tree Synthesis) software. New noise prevention techniques are applied in the
array and in the periphery: three or more independent supplies, internal decoupling,
customiszation dependent supply routing, noise filtering, skew controlled I/Os, low
swing differential I/Os, all contribute to improve the noise immunity and reduce the
emission level.
The MG2RT is supported by an advanced software environment based on industry
standards linking proprietary and commercial tools. Verilog, Modelsym and Design
Compiler are the reference front-end tools. Floor planning associated with timing-
driven layout provides a short back-end cycle.