MG2 Datasheet, PDF (1/13 Pages) ATMEL Corporation – 350K Used Gates 0.5 μm CMOS Sea of Gates

Features
• Full Range of Matrices with up to 480K Gates
• 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates
• RAM and DPRAM Compilers
• Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG)
• 3 and 5 Volts Operation; Single or Dual Supply Mode
• High Speed Performances
– 420 ps Max NAND2 Propagation Delay at 4.5V, 670 ps at 2.7 and FO = 5
– Min 650 MHz Toggle Frequency at 4.5V and 340 MHz at 2.7V
• Programmable PLL Available on Request
• High System Frequency Skew Control through Clock Tree Synthesis Software
• Low Power Consumption:
– 1.96 µW/Gate/MHz at 5V
– 0.6 µW/Gate/MHz at 3V
• Integrated Power On Reset
• Matrices With a Max of 484 Fully Programmable Pads
• Standard 3, 6, 12 and 24 mA I/Os
• Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator
• CMOS/TTL/PCI Interface
• ESD (2 KV) and Latch-up Protected I/O
• High Noise and EMC Immunity:
– I/O with Slew Rate Control
– Internal Decoupling
– Signal Filtering between Periphery and Core
– Application Dependent Supply Routing and Several Independent Supply Sources
• Wide Range of Hermetic and Plastic Packages
• Delivery in Die Form with 94.6 µm Pad Pitch
• Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout,
Power Management
• Cadence^®, Mentor^™, Vital and Synopsys^® Reference Platforms
• EDIF and VHDL Reference Formats
• Available In Commercial, Industrial and Military Quality Grades (for Space Application
see MG2RT and MG2RTP Specifications)
• QML Q with SMD 5962-00B02
350K Used Gates
0.5 µm CMOS
Sea of Gates
MG2
Description
The MG2 series is a 0.5 micron, array based, CMOS product family. Several arrays up
to 480K gates cover most system integration needs. The MG2 is manufactured using
a 0.5 micron drawn, 3 metal layers CMOS process, called SCMOS 3/2.
The base cell architecture of the MG2 series provides high routability of logic with
extremely dense compiled memories: RAM and DPRAM. ROM can be generated
using synthesis tools.
Accurate control of clock distribution can be achieved by PLL hardware and CTS
(Clock Tree Synthesis) software. New noise prevention techniques are applied in the
array and in the periphery: three or more independent supplies, internal decoupling,
customization dependent supply routing, noise filtering, skew controlled I/Os, low
swing differential I/Os, all contribute to improve the noise immunity and reduce the
emission level.
The MG2 is supported by an advanced software environment based on industry stan-
dards linking proprietary and commercial tools. Verilog, Modelsim, Design Compiler
are the reference front-end tools. Floor planning associated with timing driven layout
provides a short back-end cycle.
The MG2 library allows straight forward migration from MG1 Sea of Gates. A netlist
based on this library can be simulated as either MG2, or MG2RT or MG2RTP.
4137O–AERO–06/05