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ATF2500C Datasheet, PDF (1/20 Pages) ATMEL Corporation – ATF2500C CPLD Family Datasheet | |||
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Features
⢠High-performance, High-density, Electrically-erasable Programmable Logic Device
⢠Fully Connected Logic Array with 416 Product Terms
⢠15 ns Maximum Pin-to-pin Delay for 5V Operation
⢠24 Flexible Output Macrocells
â 48 Flip-flops â Two per Macrocell
â 72 Sum Terms
â All Flip-flops, I/O Pins Feed in Independently
⢠D- or T-type Flip-flops
⢠Product Term or Direct Input Pin Clocking
⢠Registered or Combinatorial Internal Feedback
⢠Backward Compatible with ATV2500B/BQ and ATV2500H Software
⢠Advanced Electrically-erasable Technology
â Reprogrammable
â 100% Tested
⢠44-lead Surface Mount Package and DIP Package
⢠Flexible Design: Up to 48 Buried Flip-flops and 24 Combinatorial Outputs
Simultaneously
⢠8 Synchronous Product Terms
⢠Individual Asynchronous Reset per Macrocell
⢠OE Control per Macrocell
⢠Functionality Equivalent to ATV2500B/BQ and ATV2500H
⢠2000V ESD Protection
⢠Security Fuse Feature to Protect the Code
⢠Commercial and Industrial Temperature Range Offered
⢠10 Year Data Retention
⢠Pin Keeper Option
⢠200 mA Latch-up Immunity
Block Diagram
ATF2500C
CPLD Family
Datasheet
ATF2500C
Pin Configurations
Pin Name
IN
CLK/IN
I/O
I/O 0,2,4...
I/O 1,3,5...
GND
VCC
Function
Logic Inputs
Pin Clock and Input
Bi-directional Buffers
âEvenâ I/O Buffers
âOddâ I/O Buffers
Ground
+5V Supply
DIP
CLK/IN 1
IN 2
IN 3
I/O0 4
I/O1 5
I/O2 6
I/O3 7
I/O4 8
I/O5 9
VCC 10
I/O17 11
I/O16 12
I/O15 13
I/O14 14
I/O13 15
I/O12 16
IN 17
IN 18
IN 19
IN 20
40 IN
39 IN
38 IN
37 IN
36 I/O6
35 I/O7
34 I/O8
33 I/O9
32 I/O10
31 I/O11
30 GND
29 I/O23
28 I/O22
27 I/O21
26 I/O20
25 I/O19
24 I/O18
23 IN
22 IN
21 IN
PLCC/LCC/JLCC
I/O2 7
I/O3 8
I/O4 9
I/O5 10
VCC 11
VCC 12
I/O17 13
I/O16 14
I/O15 15
I/O14 16
I/O13 17
39 I/O7
38 I/O8
37 I/O9
36 I/O10
35 I/O11
34 GND
33 GND
32 I/O23
31 I/O22
30 I/O21
29 I/O20
Note:
(PLCC/LCC/JLCC packages) pin 4 and pin 26
GND connections are not required, but are rec-
ommended for improved noise immunity.
Rev. 0777IâPLDâ4/03
1
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