ATF22V10CZ_97 Datasheet, PDF (1/13 Pages) ATMEL Corporation – High performance EE PLD

Features
• Industry-standard Architecture
• 12 ns Maximum Pin-to-pin Delay
• Zero Power – 25 µA Maximum Standby Power (Input Transition Detection)
• CMOS and TTL Compatible Inputs and Outputs
• Advanced Electrically-erasableTechnology
– Reprogrammable
– 100% Tested
• Latch Feature Holds Inputs to Previous Logic State
• High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-line and Surface Mount Standard Pinouts
• PCI Compliant
Block Diagram
High-
performance
EE PLD
ATF22V10CZ
ATF22V10CQZ
Description
The ATF22V10CZ/CQZ is a high-performance CMOS (electrically-erasable)
programmable logic device (PLD) which utilizes Atmel’s proven electrically-erasable
Pin Configurations
TSSOP
(continued)
All Pinouts Top View
Pin Name
CLK
IN
I/O
VCC
Function
Clock
Logic Inputs
Bi-directional Buffers
+5V Supply
PLCC
CLK/IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
IN 8
IN 9
IN 10
IN 11
GND 12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
IN 5
IN 6
IN 7
GND* 8
IN 9
IN 10
IN 11
25 I/O
24 I/O
23 I/O
22 GND*
21 I/O
20 I/O
19 I/O
Note:
For PLCC, P1, P8, P15 and P22 can be left
unconnected. For superior performance, con-
nect VCC to pin 1 and GND to 8, 15, and 22.
DIP/SOIC
CLK/IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
IN 8
IN 9
IN 10
IN 11
GND 12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
Rev. 0778H–03/01
1