ATF22V10CZ Datasheet, PDF (1/9 Pages) ATMEL Corporation – Highperformance EE PLD

Features
Industry Standard Architecture
• _{12 ns Maximum Pin-to-Pin Delay}
•• _{Zero Power - 25 µA Maximum Standby Power}
CMOS and TTL Compatible Inputs and Outputs
•• Advanced Electrically Erasable Technology
Reprogrammable
100% Tested
Latch Feature Holds Inputs to Previous Logic State
•• High Reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
•• _{Dual-in-Line and Surface Mount Packages in Standard Pinouts}
Block Diagram
High
Performance
E² PLD
ATF22V10CZ
Preliminary
Description
The ATF22V10CZ is a high performance CMOS (Electrically Erasable) Programma-
ble Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash mem-
ory technology. Speeds down to 12 ns with zero standby power dissipation are of-
fered. All speed ranges are specified over the full 5V ±10% range for industrial tem-
perature ranges; 5V ± 5% for commercial range 5-volt devices.
Pin Configurations
Pin Name
CLK
IN
I/O
VCC
Function
Clock
Logic Inputs
Bidirectional Buffers
+5V Supply
DIP/SOIC
PLCC Top View ⁽¹⁾
TSSOP Top View
CLK/IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
IN 8
IN 9
IN 10
IN 11
GND 12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
ATF22V10CZ
Note: 1. For PLCC, P1, P8, P15 and P22 can be left uncon-
nected. Connect VCC to pin 1 and GND to 8, 15, and
22.
Rev. 0778B/V10CZ-B–04/98