ATF22V10CQ Datasheet, PDF (1/18 Pages) ATMEL Corporation – Highperformance EE PLD

Features
• Industry-standard Architecture
– Low-cost, Easy-to-use Software Tools
• High-speed, Electrically Erasable Programmable Logic Devices
– 5 ns Maximum Pin-to-pin Delay
• CMOS- and TTL-compatible Inputs and Outputs
– Latch Feature Holds Inputs to Previous Logic States
• Pin-controlled Standby Power (10 µA Typical)
• Advanced Flash Technology
– Reprogrammable
– 100% Tested
• High-reliability CMOS Process
– 20-year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latch-up Immunity
• Dual Inline and Surface Mount Packages in Standard Pinouts
• PCI-compliant
• True Input Transition Detection “Z” and “QZ” Version
Pin Configurations
All Pinouts Top View
Pin Name Function
CLK
Clock
IN
Logic Inputs
I/O
Bi-directional Buffers
GND
Ground
VCC
+5V Supply
PD
Power-down
PLCC
IN/PD 5
IN 6
IN 7
GND* 8
IN 9
IN 10
IN 11
25 I/O
24 I/O
23 I/O
22 GND*
21 I/O
20 I/O
19 I/O
TSSOP
CLK/IN 1
IN 2
IN 3
IN/PD 4
IN 5
IN 6
IN 7
IN 8
IN 9
IN 10
IN 11
GND 12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
DIP/SOIC
CLK/IN 1
IN 2
IN 3
IN/PD 4
IN 5
IN 6
IN 7
IN 8
IN 9
IN 10
IN 11
GND 12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
Note:
For all PLCCs (except “-5”), pins 1, 8, 15 and 22 can be
left unconnected. However, if they are connected, supe-
rior performance will be achieved.
High-
performance
EE PLD
ATF22V10C
ATF22V10CQ
See separate datasheet
for ATF22V10CZ and
ATF22V10CQZ options.
Rev. 0735P–PLD–01/02
1