ATF22V10C Datasheet, PDF (1/8 Pages) ATMEL Corporation – High Performance E2 PLD

Features
• Industry Standard Architecture
Low Cost Easy-to-Use Software Tools
• High Speed Electrically Erasable Programmable Logic Devices
5 ns Maximum Pin-to-Pin Delay
• CMOS and TTL Compatible Inputs and Outputs
Latch Feature Holds Inputs to Previous Logic States
• Advanced Flash Technology
Reprogrammable
100% Tested
• High Reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
• ^{Dual-in-Line and Surface Mount Packages in Standard Pinouts}
Logic Diagram
High
Performance
E² PLD
ATF22V10C
Pin Configurations
Pin Name
CLK
IN
I/O
*
VCC
PD
Function
Clock
Logic Inputs
Bidirectional Buffers
No Internal Connection
+5V Supply
Power Down
TSSOP Top View
CLK/IN 1
IN 2
IN 3
IN/PD 4
IN 5
IN 6
IN 7
IN 8
IN 9
IN 10
IN 11
GND 12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
DIP/SOIC
PLCC
ATF22V10C
Note:
Top view
For PLCC, pins 1, 8, 15 and 22 can be left uncon-
nected. For superior performance, connect VCC
to pin 1 and ground to 8, 15, 22.
Rev. 0735C/22V10C-D–04/98