ATF20V8C Datasheet, PDF (1/3 Pages) ATMEL Corporation – High- Performance EE PLD

Features
• User-Controlled Power Down Pin
• High-Speed Equivalent of ATF20V8B
• Pin-Controlled Zero Standby Power (10 µA Typical) Option
• Industry Standard Architecture
– Emulates Many 24-Pin PALs^®
– Low-Cost Easy-to-Use Software Tools
• High-Speed Electrically-Erasable Programmable Logic Devices
– 5 ns Maximum Pin-to-Pin Delay
• CMOS and TTL Compatible Inputs and Outputs
– Latch Feature Hold Outputs to Previous Logic States
• Advanced Flash Technology
– Reprogrammable
– 100% Tested
• High-Reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Commercial, and Industrial Temperature Ranges
• Dual-in-Line and Surface Mount Packages in Standard Pinouts
• PCI Compliant
Block Diagram
High-
Performance
EE PLD
ATF20V8C
Advance
Information
Pin Configurations
Pin Name
CLK
IN
I/O
OE
*
VCC
PD
Function
Clock
Logic Inputs
Bidirectional Buffers
Output Enable
No Internal Connection
+5V Supply
Power Down
DIP
CLK/IN 1
IN 2
IN 3
PD/IN 4
IN 5
IN 6
IN 7
IN 8
IN 9
IN 10
IN 11
GND 12
24 VCC
23 IN
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 IN
13 OE/IN
TSSOP Top View
CLK/IN 1
IN 2
IN 3
PD/IN 4
IN 5
IN 6
IN 7
IN 8
IN 9
IN 10
IN 11
GND 12
24 VCC
23 IN
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 IN
13 OE/IN
PLCC Top View
PD/IN 5
IN 6
IN 7
*8
IN 9
IN 10
IN 11
25 I/O
24 I/O
23 I/O
22 *
21 I/O
20 I/O
19 I/O
Rev. 0408D–01/99
1