ATF16V8CZ_05 Datasheet, PDF (1/26 Pages) ATMEL Corporation – Highperformance EE PLD

Features
• Industry-standard Architecture
– Emulates Many 20-pin PALs
– Low-cost Easy-to-use Software Tools
• High-speed Electrically-erasable Programmable Logic Devices
– 12 ns Maximum Pin-to-pin Delay
• Low-power - 5 µA (Typ) Standby Current
• CMOS and TTL Compatible Inputs and Outputs
– Input and I/O Pin Keeper Circuits
• Advanced Flash Technology
– Reprogrammable
– 100% Tested
• High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-line and Surface Mount Packages in Standard Pinouts
• PCI-compliant
• Green (Pb/Halide-free/RoHS Compliant) Package Options Available
High-
performance
EE PLD
ATF16V8CZ
1. Description
The ATF16V8CZ is a high-performance EECMOS programmable logic device that uti-
lizes Atmel’s proven electrically-erasable Flash memory technology. Speeds down to
12 ns and a 5 µA (Typ) edge-sensing power-down mode are offered. All speed ranges
are specified over the full 5V ±10% range for industrial temperature ranges; 5V ±5%
for commercial range 5-volt devices.
The ATF16V8CZ incorporates a superset of the generic architectures, which allows
direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight out-
puts are each allocated eight product terms. Three different modes of operation,
configured automatically with software, allow highly complex logic functions to be
realized.
The ATF16V8CZ can significantly reduce total system power, thereby enhancing sys-
tem reliability and reducing power supply costs. When all the inputs and internal
nodes are not switching, supply current drops to less than 5 µA typically. This auto-
matic power-down feature (or sleep mode) allows for power savings in slow clock
systems and asynchronous applications. Also, the pin-keeper circuits eliminate the
need for internal pull-up resistors along with their attendant power consumption.
0453H–PLD–7/05