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ATF1502AS Datasheet, PDF (1/18 Pages) ATMEL Corporation – High Performance E2PROM CPLD | |||
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Features
⢠High Density, High Performance Electrically Erasable Complex Programmable Logic
Device
â 32 Macrocells
â 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
â 44 pin
â 7.5 ns Maximum Pin-to-Pin Delay
â Registered Operation Up To 125 MHz
â Enhanced Routing Resources
⢠In-System Programmability (ISP) via JTAG
⢠Flexible Logic Macrocell
â D/T/Latch Configurable Flip Flops
â Global and Individual Register Control Signals
â Global and Individual Output Enable
â Programmable Output Slew Rate
â Programmable Output Open Collector Option
â Maximum Logic utilization by burying a register with a COM output
⢠Advanced Power Management Features
â Automatic 3 mA Stand-By for âLâ Version
â Pin-Controlled 4 mA Stand-By Mode (Typical)
â Programmable Pin-Keeper Inputs and I/Os
â Reduced-Power Feature Per Macrocell
⢠Available in Commercial and Industrial Temperature Ranges
⢠Available in 44-pin PLCC; TQFP; and PQFP
⢠Advanced EEPROM Technology
â 100% Tested
â Completely Reprogrammable
â 100 Program/Erase Cycles
â 20 Year Data Retention
â 2000V ESD Protection
â 200 mA Latch-Up Immunity
⢠JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
⢠PCI-compliant
⢠3.3 or 5.0V I/O pins
⢠Security Fuse Feature
Enhanced Features
⢠Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
⢠Output Enable Product Terms
⢠D - Latch Mode
⢠Combinatorial Output with Registered Feedback within any Macrocell
⢠Three Global Clock Pins
⢠ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
⢠Fast Registered Input from Product Term
⢠Programmable âPin-Keeperâ Option
⢠VCC Power-Up Reset Option
⢠Pull-Up Option on JTAG Pins TMS and TDI
⢠Advanced Power Management Features
â Edge Controlled Power Down âLâ
â Individual Macrocell Power Option
â Disable ITD on Global Clocks, Inputs and I/O
High
Performance
E2PROM CPLD
ATF1502AS
Preliminary
Rev. 0995Aâ04/98
1
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