ATC18RHA_14 Datasheet, PDF (1/16 Pages) ATMEL Corporation – Comprehensive Library of Standard Logic and I/O Cells

Features
• Comprehensive Library of Standard Logic and I/O Cells
• Up to 6.5 usable Mgates equivalent NAND2
• Operating voltage 1.8V for core and 3.3V or 2.5V for I/O’s
• Memory Cells Compiled or synthesized to the Requirements of the Design
• EDAC Library
• Cold Sparing Buffers
• High Speed LVDS Buffers (655Mbps)
• PCI Buffers
• MQFP Package Up to 352 Pins (336 Signal Pins)
• MLGA Packages Up to 625 Pins (575 Signal Pins)
• ESD better than 2000V for I/O and better than 1000V for PLL
• Predefined Die Sizes to Accommodate Standardized Packages
• Space Multi Project Wafer - SMPW - possibility
• No single event latch-up below a LET threshold of 95 Mev/mg/cm² at 125°C
• SEU hardened flip-flops
• Tested up to a total dose of 300 krads (Si) according to Mil Std 883 Test Method 1019
• Quality Grades: QML-Q and QML-V with 5962-06B02, ESCC 9000
Rad. Hard
0.18 µm CMOS
Cell-based ASIC
for Space Use
Description
The ATC18RHA asic family provides high-performance and high-density solutions for
space applications. ATC18RHA is fabricated on a 0.18 µm, five-metal-layers CMOS
process intended for use with a supply voltage of 1.8V for core. It offers up to 6.5 mil-
lion routable gates and more than 800 pads.
The ATC18RHA family is supported by a combination of state-of-art third-party and
proprietary design tools: Synopsys, Mentor and Cadence are the reference front end
and back end tools suppliers.
The ATC18RHA asic family is available in several quality assurance grades, such as
Mil-Prf 38535 QML-Q and QML-V and ESCC 9000.
ATC18RHA
4261G–AERO–02/11