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ATC18RHA Datasheet, PDF (1/20 Pages) ATMEL Corporation – Rad. Hard 0.18 Um CMOS Cell-based ASIC for Space Use | |||
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Features
⢠Comprehensive Library of Standard Logic and I/O Cells
⢠ATC18RHA Core and IO18 pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main
Condition
⢠IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V Environments
⢠Memory Cells Compiled or synthesized to the Requirements of the Design
⢠EDAC Library
⢠SEU Hardened DFFâs
⢠Cold Sparing Buffers
⢠High Speed LVDS Buffers (655Mbps)
⢠PCI Buffers
⢠Predefined Die Sizes to Accommodate Standardized Packages and ESA (European
Space Agency) Multi-project Wafer Services
⢠MQFP Package Up to 352 Pins (336 Signal Pins)
⢠MCGA Packages Up to 625 Pins (593 Signal Pins)
⢠ESD better than 2000V
⢠Assurance Programs Allow:
â Testing Flight Models to ESCC and QML Q & V quality grades
â Monitoring Heavy Ions Latch-up Immunity and Total Dose Capability Better than
100 Krads.
Description
The ATC18RHA is fabricated on a proprietary 0.18 µm, six-metal-layers CMOS pro-
cess intended for use with a supply voltage of 1.8V ± 0.15V. Table 1 shows the range
of recommended operating conditions for which Atmel library cells have been
characterized.
Table 1. Recommended operating conditions
Symbol
Parameter
Conditions
Min Typ Max Unit
Core &
Vdd
DC supply voltage standard IOs
1.65 1.8 1.95
V
Vdd3.3
DC supply voltage 3V interface IO
3
3.3
3.6
V
Vi
DC supply voltage
0
Vdd
V
Vo
DC supply voltage
0
Vdd
V
Operating free air
Temp
temperature range Military
-55
+125 °C
The Atmel cell libraries and memory compilers have been designed and or character-
ized in order to be compatible with each other. Simulation representations exist for
three types of operating conditions. They correspond to three characterization condi-
tion sets defined as follows:
⢠MIN conditions:
â â TJ = -55°C
â â VDD (cell) = 1.95V
â â Process = fast (0.95)
⢠TYP conditions:
â â TJ = +25°C
â â VDD (cell) = 1.8V
â â Process = typical (1)
Rad. Hard
0.18 µm CMOS
Cell-based ASIC
for Space Use
ATC18RHA
4261BâAEROâ06/05
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