ATC18M Datasheet, PDF (1/8 Pages) ATMEL Corporation – 0.18 μm CMOS Cell-based ASIC for Military Use

Features
• Comprehensive Library of Standard Logic and I/O Cells
• ATC18 Core and I/O Cells Designed to Operate with V_DD = 1.8V ± 0.15V as Main Target
Operating Conditions
• IO33 Pad Libraries Provide Interfaces to 3V Environments
• Memory Cells Compiled to the Precise Requirements of the Design
• Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard-interface
and Application-specific Cells
• EDAC Library
• SEU Hardened DFF’s
• Cold Sparring Buffers
• High Speed LVDS Buffers
• PCI Buffer
• Predefined die Sizes to Easily Accommodate Specified Packages
• MQFP Packages up to 352 pins (340 Signal Pins)
• MCGA Packages up to 625 pins (581 Signal Pins)
• Offered to QML Q Grade
Description
The Atmel ATC18M is fabricated on a proprietary 0.18 µm, up to six-layer-metal
CMOS process intended for use with a supply voltage of 1.8V ± 0.15V. Table 1 shows
the range for which Atmel library cells have been characterized.
Table 1. Recommended Operating Conditions
Symbol Parameter
Conditions
V_DD
V_DD3.3
V_I
V_O
TEMP
DC Supply Voltage
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Free Air
Temperature Range
Core and Standard I/Os
3V Interface I/Os
Military
Min Typ Max Unit
1.65 1.8 1.95 V
3 3.3 3.6
V
0
V_DD
V
0
V_DD
V
-55
+125 °C
The Atmel cell libraries and megacell compilers have been designed in order to be
compatible with each other. Simulation representations exist for three types of operat-
ing conditions. They correspond to three characterization conditions defined as
follows:
• MIN conditions:
– T_J = -55°C
– V_DD (cell) = 1.95V
– Process = fast
• TYP conditions:
– T_J = +25°C
– V_DD (cell) = 1.8V
– Process = typ
• MAX conditions:
– T_J = +125°C
– V_DD (cell) = 1.65V
– Process = slow
0.18 µm CMOS
Cell-based ASIC
for Military Use
ATC18M
Advanced
Information
Rev. 4262A–AERO–07/03
1