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AT94S Datasheet, PDF (1/31 Pages) ATMEL Corporation – Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM | |||
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Features
⢠Multichip Module Containing Field Programmable System Level Integrated Circuit
(FPSLICâ¢) and Secure Configuration EEPROM Memory
⢠512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System
Programming (ISP)
⢠Field Programmable System Level Integrated Circuit (FPSLIC)
â AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core and
Extensive Data and Instruction SRAM
⢠5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAMâ¢
â 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
â High-performance DSP Optimized FPGA Core Cell
â Dynamically Reconfigurable In-System â FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic® Designs
â Very Low Static and Dynamic Power Consumption â Ideal for Portable and
Handheld Applications
⢠Patented AVR Enhanced RISC Architecture
â 120+ Powerful Instructions â Most Single Clock Cycle Execution
â High-performance Hardware Multiplier for DSP-based Systems
â Approaching 1 MIPS per MHz Performance
â C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
â Low-power Idle, Power-save, and Power-down Modes
â 100 µA Standby and Typical 2-3 mA per MHz Active
⢠Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
â Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
â Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
⢠JTAG (IEEE Std. 1149.1 Compliant) Interface
â Extensive On-chip Debugging Support
â Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)
⢠AVR Fixed Peripherals
â Industry-standard 2-wire Serial Interface
â Two Programmable Serial UARTs
â Two 8-bit Timer/Counters with Separate Prescaler and PWM
â One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
⢠Support for FPGA Custom Peripherals
â AVR Peripheral Control â Up to 16 Decoded AVR Address Lines Directly
Accessible to FPGA
â FPGA Macro Library of Custom Peripherals
⢠Up to 16 FPGA Supplied Internal Interrupts to AVR
⢠Up to Four External Interrupts to AVR
⢠8 Global FPGA Clocks
â Two FPGA Clocks Driven from AVR Logic
â FPGA Global Clock Access Available from FPGA Core
⢠Multiple Oscillator Circuits
â Programmable Watchdog Timer with On-chip Oscillator
â Oscillator to AVR Internal Clock Circuit
â Software-selectable Clock Frequency
â Oscillator to Timer/Counter for Real-time Clock
⢠VCC: 3.0V - 3.6V
⢠5V Tolerant I/O
⢠3.3V 33 MHz PCI Compliant FPGA I/O
â 20 mA Sink/Source High-performance I/O Structures
â All FPGA I/O Individually Programmable
⢠High-performance, Low-power 0.35µ CMOS Five-layer Metal Process
⢠State-of-the-art Integrated PC-based Software Suite including Co-verification
Secure
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36 Kbytes
of SRAM and
On-chip
Program
Storage
EEPROM
AT94S
Secure Series
Programmable
SLI
Rev. 2314DâFPSLIâ2/04
1
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