AT91M42800A_14 Datasheet, PDF (1/6 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

Errata Sheet V1.0
This Errata Sheet refers to:
• The following datasheets:
AT91M42800A Summary, Rev. 1779AS–06/01
AT91M42800A, Rev. 1779A–06/01
AT91M42800A, Electrical Characteristics, Rev. 1776A–08/01
• 144-lead TQFP and 144s-ball BGA devices with the following markings:
Internal Product
Reference 56544C
AT91
ARM^® Thumb^®
Microcontrollers
9. Warning: Additional NWAIT Constraints
AT91M42800A-33AI
AT91M42800A-33CI
When the NWAIT signal is asserted during an external memory access, the fol-
lowing EBI behavior is correct:
– NWAIT is asserted before the first rising edge of the master clock and
respects the NWAIT to MCKI rising setup timing as defined in the Electrical
Characteristics datasheet.
– NWAIT is sampled inactive and at least one standard wait state remains to
be executed, even if NWAIT does not meet the NWAIT to first MCKI rising
setup timing (i.e., NWAIT is asserted only on the second rising edge of
MCKI).
In these cases, the access is delayed as required by NWAIT and the access oper-
ations are correctly performed.
In other cases, the following erroneous behavior occurs:
– 32-bit read accesses are not managed correctly and the first 16-bit data
sampling takes into account only the standard wait states. 16- and 8-bit
accesses are not affected.
– During write accesses of any type, the NWE rises on the rising edge of the
last cycle as defined by the programmed number of wait states. However,
NWAIT assertion does affect the length of the total access. Only the NWE
pulse length is inaccurate.
At maximum speed, asserting the NWAIT in the first access cycle is not possible,
as the sum of the timings “MCKI Falling to Chip Select” and “NWAIT setup to
MCKI rising” are generally higher than one half of a clock period. This leads to
using at least one standard wait state. However, this is not sufficient except to per-
form byte or half-word read accesses. Word and write accesses require at least
two standard wait states.
AT91M42800A
Errata Sheet
V1.0
Rev. 1782B–01/02
1