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AT91M40800_14 Datasheet, PDF (1/4 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture
Errata Sheet V1.0
This Errata Sheet refers to:
• The following datasheets:
AT91M40800 Summary, Rev. 1348CS–05/00
AT91X40 Series, Rev. 1354C–08/01
AT91M40800 Electrical Characteristics, Rev. 1393A–08/00
• 100-lead TQFP devices with the following markings
Internal Product
Reference 56510C or 56510E
AT91
ARM® Thumb®
Microcontrollers
AT91M40800-33AI
1. Warning: Additional NWAIT Constraints
When the NWAIT signal is asserted during an external memory access, the fol-
lowing EBI behavior is correct:
– NWAIT is asserted before the first rising edge of the master clock and
respects the NWAIT to MCKI rising setup timing as defined in the Electrical
Characteristics datasheet.
– NWAIT is sampled inactive and at least one standard wait state remains to
be executed, even if NWAIT does not meet the NWAIT to first MCKI rising
setup timing (i.e., NWAIT is asserted only on the second rising edge of
MCKI).
In these cases, the access is delayed as required by NWAIT and the access oper-
ations are correctly performed.
In other cases, the following erroneous behavior occurs:
– 32-bit read accesses are not managed correctly and the first 16-bit data
sampling takes into account only the standard wait states. 16- and 8-bit
accesses are not affected.
– During write accesses of any type, the NWE rises on the rising edge of the
last cycle as defined by the programmed number of wait states. However,
NWAIT assertion does affect the length of the total access. Only the NWE
pulse length is inaccurate.
At maximum speed, asserting the NWAIT in the first access cycle is not possible,
as the sum of the timings “MCKI Falling to Chip Selec” and “NWAIT setup to MCKI
rising” are generally higher than one half of a clock period. This leads to using at
least one standard wait state. However, this is not sufficient except to perform
byte or half-word read accesses. Word and write accesses require at least two
standard wait states.
AT91M40800
Errata Sheet
V1.0
Rev. 1747A–01/02
1