AT90S8515_14 Datasheet, PDF (1/4 Pages) ATMEL Corporation – AVR – High-performance and Low-power RISC Architecture

Errata
• LDS/STS when Accessing External RAM
• STS when Accessing EEPROM
• COM1B Settings Never Disconnects OC1B
• UART Loses Synchronization if RXD Line is Low when UART Receive is Disabled
• Releasing Reset Condition without Clock
• Lock Bits at High V_CC
• The SPI Can Send Wrong Byte
• Reset during EEPROM Write
• SPI Interrupt Flag Can be Undefined after Reset
• Serial Programming at Voltages below 3.0 Volts
• Skip Instructions with Interrupts
11. LDS/STS when Accessing External RAM
Using an LDS instruction for reading external RAM corrupts the source register
used in the LDS instruction when directly followed by NOP. An STS instruction for
writing to external RAM corrupts R0 when directly followed by NOP.
Problem Fix/Workaround
Do not insert a NOP instruction directly after an LDS or STS instruction used for
accessing the external RAM.
10. STS when Accessing EEPROM
If the STS instruction is used to start an EEPROM write (EEWE in EECR), the
following instruction may have an undesired result. In the case of NOP, R0
will be corrupted.
Problem Fix/Workaround
Use the OUT or SBI instruction to start an EEPROM write.
9. COM1B Settings Never Disconnects OC1B
According to the datasheet, Timer/Counter1 should be disconnected from the
OC1B pin when COM1B[1:0] = “00” in non-PWM mode, and when
COM1B[1:0] = “00” or “01” in PWM mode. This, however, is not the case.
For OC1A, the description in the datasheet is correct; the general digital I/O func-
tion takes over.
Problem Fix/Workaround
As OC1B is an output only pin with no general digital I/O function, the pin cannot
be tri-staded. However, if there is a need to stop the pin from toggling, disable the
PWM mode by setting PWM[1:0] to “00” and set the COM1A[1:0] to anything else
than “01” (which is the toggle mode). Warning: As long as the timer is still running,
the counter can count to a value above the maximum for that PWM mode. As an
alternative, the timer can be stopped by setting CS1[2:0] in TCCR1B to “000”.
8. UART Loses Synchronization if RXD Line is Low when UART Receive is
Disabled
The UART will detect an UART start bit and start reception even if the UART is not
enabled. If this occurs, the first byte after reenabling the UART will be corrupted.
Problem Fix/Workaround
Make sure that the RX line is high at start-up and when the UART is disabled. An
external RS232-level converter keeps the line high during start-up.
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90S8515
Rev. B
Errata Sheet
Rev. 1195E–09/01
1