AT89LP4052_14 Datasheet, PDF (1/94 Pages) ATMEL Corporation – Single Clock Cycle per Byte Fetch

Features
• Compatible with MCS^®51 Products
• 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions
• Single Clock Cycle per Byte Fetch
• 2/4K Bytes of In-System Programmable (ISP) Flash Memory
– Serial Interface for Program Downloading
– 32-byte Fast Page Programming Mode
– 32-byte User Signature Array
• 2.4V to 5.5V V_CC Operating Range
• Fully Static Operation: 0 Hz to 20 MHz
• 2-level Program Memory Lock
• 256 x 8 Internal RAM
• Hardware Multiplier
• 15 Programmable I/O Lines
• Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and
Open-drain Modes
• Enhanced UART with Automatic Address Recognition and Framing Error Detection
• Enhanced SPI with Double-buffered Send/Receive
• Programmable Watchdog Timer with Software Reset
• 4-level Interrupt Priority
• Analog Comparator with Selectable Interrupt and Debouncing
• Two 16-bit Enhanced Timer/Counters with 8-bit PWM
• Brown-out Detector and Power-off Flag
• Internal Power-on Reset
• Low Power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
8-bit
Microcontroller
with 2/4-Kbyte
Flash
AT89LP2052
AT89LP4052
1. Description
The AT89LP2052/LP4052 is a low-power, high-performance CMOS 8-bit microcon-
troller with 2/4K bytes of In-System Programmable Flash memory. The device is
manufactured using Atmel's high-density nonvolatile memory technology and is com-
patible with the industry-standard MCS-51 instruction set. The AT89LP2052/LP4052
is built around an enhanced CPU core that can fetch a single byte from memory every
clock cycle. In the classic 8051 architecture, each fetch required 6 clock cycles, forc-
ing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP2052/LP4052
CPU, instructions need only 1 to 4 clock cycles providing 6 to 12 times more through-
put than the standard 8051. Seventy percent of instructions need only as many clock
cycles as they have bytes to execute, and most of the remaining instructions require
only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput
whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consump-
tion. Conversely, at the same throughput as the classic 8051, the new CPU core runs
at a much lower speed and thereby greatly reduces power consumption.
3547J–MICRO–10/09