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AT89LP213_08 Datasheet, PDF (1/96 Pages) ATMEL Corporation – 8-bit Microcontroller with 2K Bytes Flash | |||
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Features
⢠8-bit Microcontroller Compatible with MCS®51 Products
⢠Enhanced 8051 Architecture
â Single Clock Cycle per Byte Fetch
â Up to 20 MIPS Throughput at 20 MHz Clock Frequency
â Fully Static Operation: 0 Hz to 20 MHz
â On-chip 2-cycle Hardware Multiplier
â 128 x 8 Internal RAM
â 4-level Interrupt Priority
⢠Nonvolatile Program Memory
â 2K Bytes of In-System Programmable (ISP) Flash Memory
â Endurance: Minimum 10,000 Write/Erase Cycles
â Serial Interface for Program Downloading
â 32-byte Fast Page Programming Mode
â 64-byte User Signature Array
â 2-level Program Memory Lock for Software Security
⢠Peripheral Features
â Two 16-bit Enhanced Timer/Counters
â Two 8-bit PWM Outputs (AT89LP213 Only)
â Enhanced UART with Automatic Address Recognition and Framing Error
Detection (AT89LP214 Only)
â Enhanced Master/Slave SPI with Double-buffered Send/Receive
â Programmable Watchdog Timer with Software Reset
â Analog Comparator with Selectable Interrupt and Debouncing
â 8 General-purpose Interrupt Pins
⢠Special Microcontroller Features
â Two-wire On-chip Debug Interface
â Brown-out Detection and Power-on Reset with Power-off Flag
â Internal 8 MHz RC Oscillator
â Low Power Idle and Power-down Modes
â Interrupt Recovery from Power-down Mode
⢠I/O and Packages
â Up to 12 Programmable I/O Lines
â Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and
Open-drain Modes
â 5V Tolerant I/O
â 14-lead TSSOP or PDIP
⢠Operating Conditions
â 2.4V to 5.5V VCC Voltage Range
â -40° C to 85°C Temperature Range
8-bit
Microcontroller
with 2K Bytes
Flash
AT89LP213
AT89LP214
1. Description
The AT89LP213/214 is a low-power, high-performance CMOS 8-bit microcontroller
with 2K bytes of In-System Programmable Flash memory. The device is manufactured
using Atmel's high-density nonvolatile memory technology and is compatible with the
industry-standard MCS-51 instruction set. The AT89LP213/214 is built around an
enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instruc-
tions to execute in 12, 24 or 48 clock cycles. In the AT89LP213/214 CPU, instructions
3538CâMICROâ06/08
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