AT85C51SND3BX_14 Datasheet, PDF (1/4 Pages) ATMEL Corporation – Battery Monitor – Bad Conversion Linearity

Active AT85C51SND3Bx Errata List
• I/O Ports – P0, P2, P4, P5 Read-Modify-Write
• SIO Interface – Low Baudrate Data Reception Ready Report
• SPI Interface – DFC Usage Limitation
• Battery Monitor – Bad Conversion Linearity
• ISP – ISP Entry When Blanked Nand Flash
• ISP – ISP USB enumeration on Windows^™ XP
AT85C51SND3Bx Errata History
Lot Number
All
Errata List
1, 2, 3, 4, 5, 6
MP3
Microcontrollers
AT85C51SND3Bx
AT85C51SND3Bx Errata Description
Errata Sheet
1. I/O Ports – P0, P2, P4, P5 Read-Modify-Write
The P0, P2, P4, P5 implementation may lead to Input lock-up when using read-
modify-write (RMW) instructions:
ANL
(logical AND, e.g., ANL P2,A)
ORL
(logical OR, e.g., ORL P2,A)
XRL
(logical EX-OR, e.g., XRL P2,A)
JBC
(jump if bit set and clear bit, e.g., JBC P2.1, LABEL)
CPL
(complement bit, e.g., CPL P2.0)
INC
(increment, e.g., INC P2)
DEC
(decrement, e.g., DEC P2)
DJNZ
(decrement and jump if not zero, e.g., DJNZ P2, LABEL)
MOV PX.Y,C (move carry bit to bit Y of Port X)
CLR PX.Y (clear bit Y of Port X)
SETB PX.Y (set bit Y of Port X)
Here is a normal I/O port RMW execution sequence:
– Read the I/O port SFR (latch)
– Modify the data
– Write back the modified data to port SFR
Now here is what is really executed, these instructions that should read the inter-
nal latch read in fact the port data:
– Read the I/O port data
– Modify the data
– Write back the modified data to port SFR
Here is a detailed example:
P0.0 is used as input (set low by external hardware) while other P0 I/O are used
as output.
Following code may set P0.1 and leave other bits unaffected:
setb P0.1;
– before executing, P0 SFR= 1111 1101; P0 port= 1111 1100
7656A–MP3–04/07